Memory Map Utilities

The rhea package contains a framework for managing the memory-mapped control, status, and data access (most often, simply control and status). The following are various memory-map utilities and peripherals.

Command bridge

The command_bridge provides a mechanism to generate memory-mapped bus cycles from a received packet. This provides a low-level external access to the internal memory-space.

The command_bridge uses FIFOBus interface to receive command packets and a FIFOBus to send response packets. The comand_briged sends a response packet for every command packet received.

The command_bridge can be used with any external interface that can source packets to the FIFIBus interface and sink packets from a FIFOBus interface.

rhea.cores.memmap.command_bridge()

Convert a command packet to a memory-mapped bus transaction

This module will decode the incomming packet and start a bus transaction, the memmap_controller_basic is used to generate the bus transactions, it convertes the Barebone interface to the MemoryMapped interface being used.

The variable length command packet is:

00: 0xDE 01: command byte (response msb indicates error) 02: address high byte 03: address byte 04: address byte 05: address low byte 06: length of data (max length 256 bytes) 07: 0xCA # sequence number, fixed for now 08: data high byte 09: data byte 10: data byte 11: data low byte Fixed 12 byte packet currently supported, future to support block write/reads up to 256-8-4 12 - 253: write / read (big-endian) @todo: last 2 bytes crc

The total packet length is 16 + data_length

Ports:

glbl: global signals and control fifobus: FIFOBus interface, read and write path mmbus: memory-mapped bus (interface)

this module is convertible

Note, most of the memory-map peripherals in the rhea package are not designed to specific memory-space addresses. The cores are designed with a ControlStatus (control-status-object: cso) interface that contains attributes which are the control and status signals to the module. These signals are automatically assigned a location in the memory-space. When working in Python the addresses are completely abstracted away when not using the cso the addresses need to be exported from the system and used explicitly.

Example

The following is an example that connects a command_bridge to a UART.