Video interfaces

class rhea.cores.video.VideoMemory(resolution=(640, 480), color_depth=(8, 8, 8))
class rhea.cores.video.VGA(color_depth=(10, 10, 10))

LT24 LCD display driver

rhea.cores.video.lt24lcd()

A video display driver for the terasic LT24 LCD display.

This driver reads pixels from the VideoMemory interface and transfers them to the LT24 display. This hardware module (component) will also perform the initial display configuration.

(arguments == ports) :param glbl: global signals, clock, reset, enable, etc. :type glbl: Global :param vmem: video memory interface, the driver will read

pixels from this interface.
Parameters:
  • lcd (LT24Interface) – The external LT24 interface.
  • None –

RGB 5-6-5 (8080-system 16bit parallel bus)

VGA driver

In rhea.cores.video is a basic VGA driver vga_sync. This driver will read from an VideoMemory interface and generate the VGA signals to the VGA. The VGA controller is a simple circuit that generates the required VGA signals from a small number of parameters. These parameters in turn generate the video region map that defines the monitor.

The VGA driver generates a bunch of timing parameters based on the monitor attributes previously defined. The following is an example of the timing parameters generated given the parameters:

resolution: 800 x 600 refresh_rate: 60 Hz line_rate: 31250

Video parameters in ticks
period …………………… 125000000.000, 8e-09 hticks …………………… 4000.000000 vticks …………………… 2083333.333333 A: full line: …………….. 3999, (31250.00 Hz) B: horizontal pulse width: …. 500 C: horizontal back porch:…… 250 D: horizontal active: ……… 3124 E: horizontal front porch: …. 125 F: full screen ……………. 2083333, (60.00 Hz) P: vertical pulse width ……. 8000 Q: vertical back porch …….. 112833 R: all lines ……………… 1919999 S: vertical front porch ……. 42500 X: pixel clock count ………. 5.000 Z: pixel count: …………… 307200

The timing parameters are defined in clock ticks unless otherwise specified. The above has a system clock of 125MHz, the full screen (including porches) is 2083333 clock ticks @ 60 Hz. From these timing parameters the vertical sync and horizontal sync signals are generated.

rhea.cores.video.vga_sync()

The following is the generation of the signals required to drive a VGA display. This implementation is derived from the pseudo code provide here: http://hamsterworks.co.nz/mediawiki/index.php/Module_11

Well isn’t that nice - the Python/MyHDL implementation is very close to the “pseudo code”!

Also, this module is intended to be parameterizable and modular based on the desired video settings

clock.frequency - the clock used to generate the pixel
clock

video_resolution - in pixels, tVGA resolution refresh_rate - in Hz, default 60 line_rate - in Hz, default is 31,250

These parameters are attributes of the VGA monitor being driven. These can be extracted from the monitor. This driver is intended to drive a single monitor setting, i.e. it cannot be dynamically changed. The driver can be setup to drive various monitor settings during elaboration/creation.

(arguments == ports) :param glbl.clock: system synchronous clock :param glbl.reset: system reset :param vga.hsync: horizontal sync :param vga.vsync: vertical sync :param vga.red: :param vga.green: :param vga.blue: :param vmem.hpxl: horizontal pixel address :param vmem.vpxl: vertical pixel address :param vmem.red: red pixel value :param vmem.green: green pixel value :param vmem.blue: blue pixel value

Parameters:
  • resolution – video resolution
  • refresh_rate – vertical rate in Hz
  • line_rate – horizontal rate in Hz

@todo: compute the line rate based on 5% overhead and the refresh rate @todo: add optional argument where the minimum subset of the timing

parameters can be provided (in a dictionary).

VGA Timing

Examples

@todo: add examples