First In, First Out (FIFO) cores¶

Various synchronous and asynchronous FIFO implementations.

fifo_sync¶

rhea.cores.fifo.fifo_sync()¶

Synchronous FIFO This block is a basic synchronous FIFO. In many cases it is better to use the fifo_fast synchronous FIFO (lower resources).

This FIFO uses a “read acknowledge”, the read data is available on the read data bus before the read strobe is active. When the read signal is set it is acknowledging the data has been read and the next FIFO item will be available on the bus.

Parameters:	glbl (Global) – global signals, clock and reset fbus (FIFOBus) – FIFO bus interface size (int) – the size of the FIFO, the FIFO will have hold at maximum size elements.

Examples

Write and read timing:

clock:           /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/
fbus.write:      _/---\_______/-----------\___________
fbus.wrtie_data: -|D1 |-------|D2 |D3 |D4 |-----------
fbus.read:       _____________/---\___________________
fbus.read_data:           |D1    |--------------------
fbus.empty:      ---------\______/--\_________________

Usage:

fifobus = FIFOBus(width=16)
fifo_inst = fifo_sync(glbl, fifobus, size=128)

fifo_async¶

rhea.cores.fifo.fifo_async()¶

The following is a general purpose, platform independent asynchronous FIFO (dual clock domains).

Cross-clock boundary FIFO, based on: “Simulation and Synthesis Techniques for Asynchronous FIFO Design”

Typically in the “rhea” package the FIFOBus interface is used to interface with the FIFOs

fifo_fast¶

rhea.cores.fifo.fifo_fast()¶

Often small simple, synchronous, FIFOs can be implemented with specialized hardware in an FPGA (e.g. vertically chaining LUTs).

This FIFO is intended to be used for small fast FIFOs. But when used for large …

This FIFO is a small FIFO (currently fixed to 16) that is implemented to take advantage of some hardware implementations.

Typical FPGA synthesis will infer shift-register-LUT (SRL) for small synchronous FIFOs. This FIFO is implemented generically, consult the synthesis and map reports.

Arguments (ports):: glbl: global signals, clock and reset fbus: FIFOBus FIFO interface

Parameters:	use_slr_prim – this parameter indicates to use the SRL primitive (inferrable primitive). If SRL are not inferred from the generic description this option can be used. Note, srl_prim will only use a size (FIFO depth) of 16.

fifo_ramp¶

rhea.cores.fifo.fifo_ramp()¶: FIFO Ramp module This module provides a simple 8-bit counter that will generate a ramp. This ramp is fed to the USB fifo. This can be used to validate the usb connection and the device to host (IN) data rates.

fifo_tester¶

WIP