Serial Peripheral Interface (SPI)

The following is a description of the SPI cores in the rhea package.

SPI controller

rhea.cores.spi.spi_controller()

SPI (Serial Peripheral Interface) module This module is an SPI controller (master) and can be used to interface with various external SPI devices.

Parameters:

• glbl (Global) – clock and reset interface
• spibus (SPIBus) – external (off-chip) SPI bus
• fifobus (FIFOBus) – interface to the FIFOs, write side is to the TX the read side from the RX.
• mmbus (MemoryMapped) – a memory-mapped bus used to access the control-status signals.
• cso (ControlStatus) – the control-status object used to control this peripheral
• include_fifo (bool) – include the FIFO … this is not fully implemented

Note

At last check the register-file automation was not complete, only the cso external control or cso configuration can be utilized.

SPI slave FIFO

rhea.cores.spi.spi_slave_fifo()

This is an SPI slave peripheral, when the master starts clocking any data in the TX FIFO (fifobus.write) will be sent (the next byte) and the received byte will be copied to RX FIFO (fifobus.read). The cso interface can be used to configure how the SPI slave peripheral behaves.

(Arguments == Ports) :param glbl: global clock and reset :type glbl: Global :param spibus: the external SPI interface :type spibus: SPIBus :param fifobus: the fifo interface :type fifobus: FIFOBus :param cso: the control status signals :type cso: ControlStatus