Memory mapped interfaces

Base classes

The following are the building blocks for defining a system with memory-mapped attributes.

class rhea.system.MemorySpace
class rhea.system.MemoryMapped(glbl=None, data_width=8, address_width=16)
acktrans(data=None)

Acknowledge transaction

add = <myhdl._block._bound_function_wrapper object>
add_csr(csr, name='')
get_generic()

Get the generic bus interface Return the object that map_to_generic maps to. :return: generic bus interface

interconnect()

Connect all the components

map_from_generic(generic)

Map the generic bus (Barebone) to this bus This is a bus adapter that will adapt the generic bus to this bus. This is a module and returns myhdl generators

Parameters:
  • generic (The generic memory-mapped bus, all the memory-mapped) –
  • modules use the generic bus internally. This provides (supported) –
  • agnostic bus interface to all the modules. (an) –
Returns:
Return type:

myhdl generators
map_to_generic(generic)

Map this bus to the generic (Barebone) bus This is a bus adapter, it will adapt the :return: generic bus, myhdl generators

peripheral_regfile(regfile, name, base_address=0)

override

Parameters:
  • glbl (global signals, clock and reset) –
  • regfile (register file interfacing to) –

:param : :type : param glbl: global signals, clock and reset :param : :type : param regfile: register file interfacing to. :param : :type : param name: name of this interface :param : :type : param base_address: base address for this register file :param : :type : return: myhdl generators

readtrans(addr)

Read transaction

writetrans(addr, data)

Write transaction

class rhea.system.MemoryMap
class rhea.system.RegisterFile(regdef=None)

Memory mapped buses

The following are the memory-mapped bus interfaces available in rhea.