avalon

Note

Avalon bus needs additional documentation…

class rhea.system.memmap.AvalonMM(glbl=None, data_width=8, address_width=16, name=None)

acktrans(data=None)

Acknowledge transaction

interconnect = <myhdl._block._bound_function_wrapper object>

peripheral_regfile = <myhdl._block._bound_function_wrapper object>

readtrans(addr)

read accessor for testbenches :param addr: :return:

writetrans(addr, val)

write accessor for testbenches :param addr: address to write :param val: value to write to the address :return: yields