wishbone

Note

Wishbone bus needs additional documentation…

class rhea.system.memmap.Wishbone(glbl=None, data_width=8, address_width=16, name=None)

acktrans(data=None)

acknowledge accessor for testbenches :param data: :return:

get_generic()

Get the generic bus interface Return the object that map_to_generic maps to. :return: generic bus interface

interconnect = <myhdl._block._bound_function_wrapper object>

peripheral_regfile = <myhdl._block._bound_function_wrapper object>

readtrans(addr)

read accessor for testbenches

writetrans(addr, val)

write accessor for testbenches Not convertible.