barebone

Note

Barebone bus needs additional documentation…

class rhea.system.memmap.Barebone(glbl, data_width=8, address_width=8, name=None, num_peripherals=16)

acktrans(data=None)

Acknowledge transaction

get_generic()

Get the generic bus interface Return the object that map_to_generic maps to. :return: generic bus interface

interconnect()

Returns:

map_from_generic(generic)

In this case the this is the generic bus, use the signals passed, that is the expected behavior.

Parameters:generic – the generic bus to map from

map_to_generic(generic)

In this case this is the generic bus, there is no mapping that needs to be done. Simply return ourself and all is good.

peripheral_regfile(glbl, regfile, name, base_address=0)

(arguments == ports) :param glbl: global signals, clock, reset, enable, etc. :param regfile: register file :param name: :param base_address:

readtrans(addr)

Read transaction

writetrans(addr, data)

Write transaction