AXI4

Note

AXI4 bus needs additional documentation…

class rhea.system.memmap.AXI4Lite(glbl, data_width=8, address_width=16)

acktrans(data=None)

Acknowledge transaction

readtrans(addr)

Read transaction

writetrans(addr, val)

Emulate a write transfer from a master The following is a very basic write transaction, future enhancements are needed to verify/validate of features of the AXI4Lite bus.

@todo: add priority (not often used) @todo: add byte strobe @todo: add response checks @todo: and checks for all channel acks